1. Field of the Invention
The present invention pertains to the field of microprocessor architecture. More particularly, this invention relates to combining data paths in a microprocessor.
2. Background
As the computer revolution has progressed the quest of microprocessor developers has been to develop chips exhibiting more power and faster performance. Initial efforts focused essentially on increasing transistor populations on single microprocessor integrated circuits. That effort continues with today's microprocessors now housing literally millions of transistors on a single chip. Further integration has allowed processor clock speeds to be greatly increased with the increased density of transistors.
Given the large number of transistors involved, modem microprocessors are divided into discrete functional blocks through which instructions are propagated one stage at a time. This allows for pipelining of instructions such that when one instruction has completed the first stage of processing and moves on to the second stage, a second instruction can begin the first stage. Thus, even where each instruction requires a number of clock cycles to complete all stages of processing, pipelining provides for the completion of instructions on every clock cycle. This single-cycle throughput of a pipelined microprocessor greatly increases the overall performance of computer systems.
Other enhancements to microprocessor design include the development of superscalar microprocessors which are capable of initiating more than one instruction at the initial stage of the pipeline per clock cycle. Likewise, in a superscalar microprocessor, frequently more than one instruction completes on a given clock cycle. Other development efforts have gone into the simplification of microprocessor instruction sets, developing reduced instruction set computer (RISC) microprocessors which exploit the fact that many simple instructions are more commonly executed than some complicated instructions. Eliminating the complicated instructions from the instruction set provides for a faster executing pipeline. Complicated instructions are carried out by combinations of the more simple instructions.
Substantial increases in instruction throughput are achievable by implementing out-of-order dispatch of instructions to the execution units of superscalar microprocessors. Many experiments have confirmed that typical Von Neumann code provides substantial parallelism and hence a potential performance boost by use of out-of-order execution. Out-of-order execution is possible when a given instruction does not depend on previous instructions for a result before executing. With out-of-order execution, any number of instructions are allowed to be executing in the execution units, up to the total number of pipeline stages for all the functional units.
Microprocessors execute a wide range of instructions based on various types of numbers, typically referred to as either floating point numbers or integer numbers. One method of executing floating point and integer instructions has been to use two different data paths for the instruction operands: one for floating point operations and the second for integer operations. These two different data paths and their corresponding control logic can be included on the same chip, or may be two physically separate chips. This separation of data paths for different operands, however, can require a large amount of chip area due to the duplication of registers to store the two types of data as well as duplicated control logic. Thus, it would be beneficial to provide a mechanism for overlapping multiple operand types in a microprocessor.
An additional enhancement to microprocessor performance is the data path width. Microprocessor integer data paths have grown in width to 32-bit and 64-bit data paths which are common today. Floating point data paths are even wider, typically being at least twice as wide as integer data paths. This large number of bits being routed around the chip requires significant chip area. Thus, it would be beneficial to provide a mechanism for overlapping multiple operand types and thereby reducing the amount of area required on a chip to support both floating point and integer data paths.
Additionally, different instructions of a typical instruction set require different numbers of operands, such as one, two or three operands. The additional data required for the three-operand instruction can result in significant additional chip area. Thus, it would be beneficial to provide a mechanism which supports instructions requiring different numbers of operands without requiring significant additional chip area and with little, if any, performance loss.
As will be described in more detail below, the present invention provides a mechanism for efficiently overlapping multiple operand types in a microprocessor that achieves these and other desired results which will be apparent to those skilled in the art from the description to follow.